brAIn · true randomness, generated in hardware

Randomness isn't computed here. It's measured.

LoMaRe's circuit turns randomness into a tunable distribution — the sampler that probabilistic compute has been imitating in software.

Every chip that needs randomness today fakes it. This one makes it.
One IP platform · four applications
True random number generation · edge AI · robotics · compute-in-memory AI inference acceleration.
01 · True random number generation

Every secure chip needs true randomness.

Keys, nonces and signatures are only ever as strong as the entropy behind them. brAIn is a drop-in hardware entropy source — the block that sits at the root of every secure chip. Developed in a standard chip process at room temperature, it integrates into secure elements, MCUs and HSMs — at orders of magnitude lower energy per bit than existing entropy circuits. Quantum resistance by design — ready for the post-quantum cyber security era.

No root number to steal, no formula to break — unpredictable by design, impossible to crack.
02 · Edge AI

In uncontrolled environments, uncertainty is the workload.

Confidence costs compute, so most edge devices skip it — and act on guesses they cannot grade. Modern policies generate each action by sampling, step by step; that sampling is exactly what brAIn does natively — accelerated, not emulated. Knowing when it does not know becomes affordable: many more possibilities per watt, or the same accuracy on a fraction of the power.

~10 femtojoules per sample — orders of magnitude below software.
03 · Robotics

Weigh thousands of possibilities — on a power budget.

A robot in a field or a human space cannot be pre-programmed. Working out where it is, it tracks thousands of possible positions at once from noisy sensors, every cycle. Deciding what to do next, it tests thousands of candidate moves per second to pick one that will not hit anything. With brAIn every one of those possibilities is a device, not an arithmetic workload — more options explored in the same budget, better choices in clutter.

memristor current · stress / sense pulses
Knowing its doubt is affordable — so it is safe near people.
04 · Compute-in-memory AI inference acceleration

Probabilistic inference, accelerated in memory.

Edge to datacenter: a compute-in-memory architecture with randomness and compute in a single array runs sampling-bound AI natively — Monte-Carlo, Bayesian and generative sampling, not emulated — at a fraction of a GPU's energy. It targets the memory-bound decode stage of inference, where the industry runs memory-light accelerators, and is delivered as licensable IP or silicon (PCIe accelerator cards).

difference of two reads → bit stream
sense
condition
feedback
Monte-Carlo, Bayesian and generative sampling — native, not emulated.
05 · One platform

One Platform. Three Markets.

The same sampler serves all three: certified entropy at the root of every secure chip, uncertainty-aware edge AI (including robotics, wearable, medical devices and others) that weigh thousands of possibilities per cycle, and compute-in-memory inference acceleration from the edge to the datacenter — one IP, delivered as licensable IP or silicon.

set Aset Bset Clive: set —
Calibrated, not just random — shaped to the probability a machine needs.
06 · Why now

AI is now limited by power — and we hand it back.

As power becomes the constraint, energy per bit becomes the product. We start from the most efficient primitive: >100× lower energy, measured in silicon — ~10 femtojoules per true-random sample, orders of magnitude below software, measured on real devices. The whole industry is racing to cut energy per bit. We begin there by construction — true randomness in silicon, at a fraction of a GPU's energy.

~£100k and ~100 tonnes CO₂ saved per site, per year (illustrative).
Heat spreaderlid
Host computedigital · unchanged · reads belief · interrupt
Conditioning · calibrationanalogue posterior accumulator · A(z) B(z) C(z) D(z)
1T1R sampler arrayM memristive generators
Substratepulse source · I/O
Vpulse · SW₁stress / sense
RMmemristor
R₁sense → I/V
I/V
A(z)
Σ⁻x(n) − x(n−1)
B(z)
t(n) ⊳ bit
C(z) · D(z)feedback
p(β)output histogram
pulses 0
bits 0
P(1) 0.50
ȳ 0.000 · σ 0.000
STRESS · SENSE · COMPARE
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Applications

Where it matters.

One IP platform, three applications — the same primitive that secures a key can weigh a robot's next move and run sampling-bound inference without the energy bill.

Why it matters

Sampling isn't the bottleneck. Simulating it is.

Probabilistic workloads are expensive on conventional hardware because randomness has to be manufactured — a PRNG, floating-point arithmetic and memory traffic for every sample. A memristor pulsed on the microsecond scale answers unrepeatably; brAIn calibrates that physical randomness into a controllable sampling operation, so the posterior can be accumulated by physics instead of computed by logic.

Because the belief lives in analogue, always-on sensing costs what a pulse costs — microwatts, continuous — and the expensive digital stages stay asleep until a decision is actually due. The digital host is untouched: it receives a belief and an interrupt, and runs whatever model it already runs.

Building a product that needs true randomness?

Talk to us about brAIn — for secure chips, edge AI, robotics or inference acceleration. Evaluation, licensing, or a joint development programme.

Get in touch